Systems Design Using VHDL Language – VGTU

About this course

Digital system description languages VHDL, Verilog and SystemC. System design and modeling at structural, register transfer and functional levels. Designed systems analysis and synthesis using ASIC or programmable logic technological libraries. System testbench implementation using VHDL, Verilog and SystemC language features. Top-down design strategy. Bottom-up design strategy. Mixed design strategies. Complex system design and implementation using different design strategies. Practical digital system architectures, components, internal communication, design tools, implementation problems and testing. Digital system analysis and defect detection.

Expected learning outcomes

The students will learn digital system design languages such as VHDL, Verilog, and SystemC, and they will use these languages to design and implement complex digital devices.

Indicative Syllabus

Systems Design Using VHDL Language

Teaching / Learning Methodology

TBA

Recommended Reading

TBA